Multilayer circuit board, process of manufacturing same, board for multilayer circuitry, and electronic apparatus

ABSTRACT

A multilayer circuit board including a laminate of at least one insulating layer and at least one wiring layer. The wiring layer is formed by a composite member having a first metal layer and a second metal layer formed on one or both sides of the first metal layer. The first metal layer having a smaller coefficient of thermal expansion than the second metal layer. The second metal layer having a higher electric conductivity than the first metal layer. The insulating layer has a blind via-hole with a bottom provided by a surface of the second metal layer. A layer-to-layer interconnection portion is provided on the surface of the insulating layer and in the blind via-hole and is formed in the blind via-hole to be in contact with the surface of the second metal layer.

The present application is a divisional application of application Ser.No. 10/445,000, filed May 27, 2003, the contents of which areincorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to a novel low thermal-expansionmultilayer circuit board suitable for the mounting of semiconductordevices, a method of manufacturing the same, a substrate for multilayercircuits, and an electronic apparatus.

2. Background Art

In recent years, semiconductor chips are often mounted directly oncircuit boards by the so-called bear chip mounting technique, wherebymounting takes place directly without the use of leaded package.However, because the coefficient of thermal expansion of semiconductordevices differs from that of circuit boards, cracks or peeling can occurin the solder-connected portions linking semiconductor devices andcircuit boards. This occurs due to temperature changes that result whenthe electronic equipment on which a circuit board is mounted isactivated, leading to faulty electrical connections. In order to bringthe coefficient of thermal expansion of the circuit board closer to thatof the semiconductor devices, a metal-core substrate has been adopted inwhich a plate of an alloy with a small coefficient of thermal expansionis laid.

Iron-nickel alloys with a nickel content of about 36–42 mass % are oftenused for the alloy plate. This is because their coefficient of thermalexpansion is about 1–5×10⁻⁶/° C., which is on the same order as thecoefficient of thermal expansion of silicon in the semiconductordevices, which is about 3×10⁻⁶/° C. While the iron-nickel alloy formingthe core is electrically insulated from the circuit in a typicalmetal-core substrate, it is sometimes used as a power supply or groundcircuit. However, the iron-nickel alloys are not suitable for use incircuits because their electric conductivity is low.

JP Patent Publication (Unexamined Application) No. 6-85414 discloses theuse of a composite member comprising an iron-nickel alloy coated bycopper on either side in a printed circuit board. The publication,however, does not describe layer-to-layer interconnection.

JP Patent Publication (Unexamined Application) No. 11-354684 disclosesthe formation of a composite member in which an iron-nickel alloy coatedwith copper on one side is stacked via a polyimide-resin insulatinglayer. While the publication also describes through-hole via-holes, thelayer-to-layer interconnection is carried out by soldering.

JP Patent Publication (Unexamined Application) Nos. 5-251868, 9-162550,11-261236, and 2001-342574 each disclose multilayer circuit boardshaving blind via-holes communicated to the wiring layer, where a circuitpattern is formed in the non-through holes.

None of the publications, however, disclose the formation oflayer-to-layer interconnections in a low expansion multilayer wiringboard comprising an iron-nickel alloy composite member formed withcopper plating. Further, the publication in which a circuit pattern isformed in blind via-holes does not disclose a low expansion wiringboard. While JP Publication (Unexamined Application) No. 2001-342574discloses the example of an iron-nickel alloy in the core substrate, itdoes not describe the wiring of the iron-nickel alloy and itslayer-to-layer interconnection.

JP Patent Publication (Unexamined Application) No. 11-354684 does notdisclose the formation of outer-layer wiring on the insulator surface byplating.

SUMMARY OF THE INVENTION

It is an object of the invention to provide a multilayer circuit boardhaving a high level of reliability against temperature changes in theelectronic equipment during operation in terms of electrical connectionsbetween layers, a process of manufacturing the same, a substrate formultilayer circuits, and an electronic apparatus. In one aspect, theinvention provides a multilayer circuit board comprising a laminate ofat least one insulating layer and at least one wiring layer, wherein thewiring layer is formed by a composite member comprising a first metallayer and a second metal layer formed on one or both sides of the firstmetal layer, the first metal layer having a smaller coefficient ofthermal expansion than the second metal layer, the second metal layerhaving a higher electric conductivity than the first metal layer,wherein the insulating layer has a blind via-hole whose bottom portionis formed by a surface of the second metal layer, the circuit boardfurther comprising a layer-to-layer interconnection portion on thesurface of the insulating layer and in the blind via-hole, wherein thelayer-to-layer interconnection portion in the blind via-hole is formedin such a manner as to be in contact with the surface of the secondmetal layer.

In another aspect, the invention provides a multilayer circuit boardcomprising at least one wiring layer formed in insulating layers,wherein the wiring layer is formed by a composite member comprising afirst metal layer and a second metal layer formed on either side of thefirst metal layer, the first metal layer having a smaller coefficient ofthermal expansion than the second metal layer, the second metal layerhaving a higher electric conductivity than the first metal layer,wherein each of the insulating layers separated by the wiring layer hasa blind via-hole whose bottom portion is formed by a surface of thesecond metal layer where the insulating layers face one another via thewiring layer, wherein the circuit board further comprises alayer-to-layer interconnection portion on the surface of the insulatinglayer and in the blind via-hole, wherein the layer-to-layerinterconnection portion in each blind via-hole is formed in such amanner as to be in contact with the second metal layer surface.

Preferably, the first metal layer comprises an alloy or an iron-nickelalloy layer having a thermal expansion coefficient of not more than10×10⁻⁶/° C., preferably from 2 to 5×10⁻⁶/° C. The iron-nickel alloylayer is either 42 alloy, which is an iron alloy containing 27–50 mass %of nickel, or covar, which is an alloy in which the nickel issubstituted with 20 mass % of cobalt. The second metal layer ispreferably copper.

In yet another aspect, the invention provides a process of manufacturinga multilayer circuit board in which at least one insulating layer and atleast one wiring layer are laminated, the process comprising the stepsof:

forming a wiring on the wiring layer in a composite member comprisingthe wiring layer and the insulating layer integrally formed on thewiring layer, the wiring layer comprising a second metal layer formed onone or both sides of a first metal layer, wherein the second metal layerhas a larger coefficient of thermal expansion than the first metallayer;

forming a blind via-hole in the insulating layer such that a bottomportion of the via-hole is formed by a surface of the second metallayer;

forming a layer-to-layer interconnection portion on the surface of theinsulating layer and in the blind via-hole in such a manner as to be incontact with the second metal layer surface that forms the blindvia-hole bottom portion.

In yet another aspect, the invention provides a process of manufacturinga multilayer circuit board comprising an insulating layer in which atleast one wiring layer is formed, the process comprising the steps of:

forming a wiring on the wiring layer in a composite member comprisingthe wiring layer and the insulating layer integrally formed on thewiring layer, the wiring layer comprising a second metal layer formed onone or both sides of a first metal layer, wherein the second metal layerhas a larger coefficient of thermal expansion than the first metallayer;

forming a blind via-hole in each insulating layer where the insulatinglayers are opposite one another via the wiring layer, the blind via-holehaving a bottom portion formed by a surface of the second metal layer;and

forming a layer-to-layer interconnection portion on the surface of theinsulating layers and in each blind via-hole in such a manner as to bein contact with the second metal layer surface forming the blindvia-hole bottom portion.

In a further aspect, the invention provides a process of manufacturing amultilayer circuit board comprising the steps of:

preparing a wiring layer formed by a composite member comprising a firstmetal layer and a second metal layer formed on one or both sides of thefirst metal layer, the second metal layer having a higher electricconductivity and a greater coefficient of thermal expansion than thefirst metal layer;

forming a substrate for multilayer circuitry by laminating the wiringlayer on one or both sides of an insulating resin layer;

forming a predetermined wiring on the wiring layer;

covering the wiring formed in the wiring forming step with an insulatinglayer;

forming a blind via-hole in the insulating layer, or the insulatinglayer and insulating resin layer, the blind via-hole having a bottomportion formed by a surface of the second metal layer; and

forming a layer-to-layer interconnection portion on the surface of theinsulating layer and in the blind via-hole in such a manner as to be incontact with the second metal layer surface in the blind via-hole.

In a further aspect, the invention provides a process of manufacturing amultilayer circuit board comprising the steps of:

preparing a wiring layer formed by a composite member comprising a firstmetal layer and a second metal layer formed on both sides of the firstmetal layer, the second metal layer having a higher electricconductivity and a greater coefficient of thermal expansion than thefirst metal layer;

forming a substrate for multilayer circuitry by laminating the wiringlayer on both sides of an insulating layer;

forming a predetermined wiring on the wiring layer formed in the wiringpreparing step;

covering the wiring formed in the wiring forming step with an insulatinglayer;

forming a blind via-hole in each insulating layer, or the insulatinglayer and insulating resin layer on the opposite surfaces between whichthe insulation layer is inserted, the blind via-hole having a bottomportion formed by a surface of the second metal layer; and

forming a layer-to-layer interconnection portion on the surface of theinsulating layer and in the blind via-hole in such a manner as to be incontact with the surface of the second metal layer in each blindvia-hole.

In a further aspect, the invention provides a substrate for multilayercircuitry comprising a composite member comprising a first metal layerand a second metal layer formed on one or both sides of the first metallayer, the composite member thermally glued under pressure to one orboth sides of an insulating resin film, wherein the first metal layerhas a smaller coefficient of thermal expansion than the second metallayer, which has a higher electric conductivity than the first metallayer. The invention also relates to a substrate for multilayercircuitry comprising a composite board comprising an iron-nickel alloyfoil having a copper layer formed on both sides thereof, the compositeboard thermally glued under pressure to one or both sides of aninsulating resin film.

In a further aspect, the invention provides a bare chip-mountedelectronic apparatus comprising a multilayer circuit board comprising alaminate of at least one insulating resin layer and at least one wiringlayer, on which substrate semiconductor devices are directly bonded,wherein the multilayer circuit board comprises the multilayer circuitboard described above or is from the process described above.

The copper layer may be deposited on the iron-nickel alloy layer byelectric plating or sputtering. Alternatively, a copper foilmanufactured by electrolysis or metal rolling may be mechanicallyattached to the iron-nickel alloy under pressure. The step of forming acopper layer on the iron-nickel alloy layer may be performed after aninsulating resin is laminated on the iron-nickel alloy beforehand. Thelayers may be laminated in the circuit board by a single batch processor by a build-up process. The blind via-hole may be formed by laser,plasma, or a drill. When a photosensitive insulating resin is employed,the via-hole may be formed by a process involving exposure to light anddeveloping.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a cross-section illustrating the manner in which the layersare electrically connected according to the invention.

FIG. 2 shows a cross-section illustrating the manner in which the layersare electrically connected according to the invention.

FIG. 3 illustrates the flow of a process of manufacturing a multilayercircuit board according to the invention.

FIG. 4 illustrates the flow of a process of manufacturing anothermultilayer circuit board according to the invention.

FIG. 5 illustrates the flow of a process of manufacturing anothermultilayer circuit board in a comparative example.

FIG. 6 illustrates the manner in which the layers are electricallyconnected in a comparative example.

FIG. 7 shows a plan view of the multilayer circuit board according tothe invention.

FIG. 8 shows a cross-section of an electronic apparatus according to theinvention.

DESCRIPTION OF THE INVENTION

The invention will be hereafter described in detail by way ofembodiments. The invention, however, is not limited to such embodiments.

Embodiment 1

FIG. 1 shows a cross-section of the multilayer circuit board accordingto the invention, in which a layer-to-layer connection portion is formedon one side of a composite board. In the present embodiment, thelayer-to-layer connection portion is formed by copper plating 6, whichis disposed in such a manner as to not be directly connected to aniron-nickel alloy. Specifically, a shown in FIG. 1, the plating 6 is inclose contact with the surface of copper 4, such that the plating 6 isin contact with the copper 4 as the second metal layer covering acomposite member 2, at the bottom of a blind via-hole 5. Thus, theplating 6 and the iron-nickel alloy 3 as the first metal layer are notin direct close contact with one another. In the example shown in FIG.1, it is assumed that a circuit comprising the plating 6 or thecomposite member 2 exists in at least one of the inner layers of themultilayer circuit board. However, the plating 6 and the compositemember 2 according to the invention may be used in either the inner orthe outer layer. The composite member 2 is a foil with a thickness ofabout 80 μm, which is produced by flat-rolling a copper layer on oneside of a layer of 42 alloy, which is an iron-nickel alloy containing 42mass % of nickel, as will be described later, or a layer of covar, whichis an iron-nickel alloy containing 29 mass % of nickel and 17 mass % ofcobalt. An insulating resin layer 1 and the composite member 2 areintegrated by heat-pressing with a vacuum press, as will be describedlater. After the insulating resin layer 7 is provided, a blind via-hole5 is drilled by a carbon-dioxide gas laser drilling machine. Then, thecopper plating 6 is formed in a manner that will be described later, andfurther predetermined circuit wiring is formed.

Thus, by adopting a structure in which the iron-nickel alloy in thecomposite member does not directly come into close contact with theplating for providing electrical connection between the layers, amultilayer circuit board is created that can maintain a high level ofreliability in terms of electrical connection between the layers evenwhen exposed to temperature changes brought about by the activation ofthe electric equipment.

Embodiment 2

FIG. 2 shows a cross-section of the multilayer circuit board accordingto the invention. The manufacturing process for the multilayer circuitboard is the same as that for Embodiment 3. In a four-layer circuitboard in which inner-layer circuits are formed by composite members 8and outer-layer circuits are formed by plating 13, when connecting oneof the inner-layer circuits to the outer layers on both sides, thecomposite member 8 comprising a first metal layer of iron-nickel alloy 9coated by a second metal layer of copper 10 on both sides is employedsuch that the copper 10 is in close contact with the plating 13 at thebottom of the blind via holes 11 and 12. Thus, the plating 13 and theiron-nickel alloy 9 do not come into direct contact with one another.Thus, by adopting a structure where the iron-nickel alloy in thecomposite member does not directly come into close contact with theplating providing electric connection between the layers, a multilayercircuit board can be provided that can maintain a high level ofreliability in terms of electrical connection between the layers, evenwhen exposed to temperature changes caused by the activation of theelectric equipment.

When through-holes are drilled in the iron-nickel alloy with a drillbit, the life of the drill bit is shortened. This problem can beovercome by the present invention, which does not require the drillingof through-holes. Further, the invention does not require theiron-nickel alloy to be exposed on the inner wall of the blind via-hole,nor does it require the cross-section of the iron-nickel alloy to becopper-plated. Thus, there is no need to perform special pre-processesfor the copper plating, greatly contributing to cost reduction andimproved yield.

Embodiment 3

FIG. 3 shows a cross-section of the manufacturing process for amultilayer circuit board according to the invention. Embodiment 3concerns a four-layer circuit board in which an inner-layer circuit isformed by a composite member and an outer-layer circuit is formed byplating.

Initially, an iron-nickel alloy 14 as a first metal layer having athickness of about 100 μm was prepared by cutting an iron-nickel alloy(YEF42 by Hitachi Metals, Ltd.) into desired dimensions (FIG. 3( a)).

Then, the iron-nickel alloy 14 was subjected to a dipping treatment in adegreasing solution (50 ml/L-METACLEAR CL-5513, by Dai-chi Kogyo SeiyakuCo., Ltd.) at 60° C. for two minutes and then washed with water. Theiron-nickel alloy 14 was then subjected to a dipping treatment in apolishing solution (250 ml/L-CPL-200, by Mitsubishi Gas ChemicalCompany) at 30° C. for one minute. After washing with water, the alloywas subjected to a dipping treatment in an activator (300ml/L-hydrochloric acid) at 25° C. for 30 seconds, and then washed withwater. Then, the alloy was copper-plated with a copper sulfate platingsolution (an additive 0.2 ml/L-CC-1220, by Nikko Metal Plating Co.,Ltd.) at 25° C. for 10 minutes, with the current density of 2.5 A/dm².After washing with water, the alloy was dried in a drying furnace at100° C. for 30 minutes, thus forming a composite member 16 coated bycopper 15 with a thickness of about 5 μm as a second metal layer oneither side thereof (FIG. 3( b)).

Then, the composite member 16 was set on each side of a polyimide film(UPILEX VT by Ube Industries. Ltd.) of a thickness of about 50 μm andpressed using a vacuum press at 350° C. under the pressure of 6 MPa for10 minutes, thereby obtaining a metal foil base member 18 (FIG. 3( c)).

Thereafter, an etching resist (H-9025K by Hitachi Chemical Co., Ltd.)was laminated on either side of the base member 18 at 110° C. Then afilm mask was placed on the resist on each side of the base member in aclose-contact manner. The mask was then irradiated with ultravioletlight from an ultra-high pressure mercury lamp at the rate of 120mJ/cm². The base member was then sprayed with a developing solution (10g/L-sodium carbonate) at 30° C. under the pressure of 0.1 MPa for 20seconds. After washing with water, the base member was sprayed with anetching solution (250 g/L-copper (II) chloride dehydrate, 200ml/L-hydrochloric acid) at 50° C. for two minutes under the pressure of2 MPa. After washing with water, the base member was sprayed with aresist removal solution (30 g/L-sodium hydroxide) at 40° C. for 30seconds under the pressure of 0.1 MPa in order to remove the dry filmresist. The base member was then washed with water and dried, therebyforming an inner-layer circuit 19 (FIG. 3( d)).

Thereafter, a polyimide film (UPILEX VT by Ube Industries. Ltd.) of athickness of about 50 μm was set on either side of the base memberhaving the inner-layer circuit 19 formed as shown in FIG. 3( d), thefilm having an electroplated copper foil (SLP-18 by Nippon Denkai, Ltd.)with a thickness of about 18 μm on one side thereof. The base member andthe film were then press-laminated using a vacuum press (VHI-1624 byKitagawa Seiki Co., Ltd.) at 350° C. for 10 minutes under the pressureof 6 MPa. The laminate was then sprayed with an etching solution (250g/L-copper (II) chloride dehydrate, 200 ml/L-hydrochloric acid) at 50°C. for 30 seconds under the pressure of 0.2 MPa. After washing withwater and drying, the electroplated copper foil on either surface wasremoved, thereby forming an insulating layer 20 that is very closelyadhered to each surface (FIG. 3( e)).

Then, a blind via-hole 21 of about φ100 μm was drilled using acarbon-dioxide gas laser drilling machine such that the via-hole reachesthe surface of the copper 15 without penetrating the composite member16. The laminate was then treated with a desmearing solution (MLB-497 byMeltex, Inc.) at 70° C. for three minutes, washed with water, treatedwith a neutralizer (MLB-790 by Meltex, Inc.) at 60° C. for five minutes,and then washed with water. The laminate was further treated with aplating catalysis solution (HS-202B by Hitachi Chemical Co., Ltd.) at25° C. for five minutes. After washing with water, the laminate wasdried, whereby a plating catalyst was attached on the laminate. This wasfollowed by a treatment in an activator (100 ml/L-sulfuric acid) at 25°C. for 30 seconds. After washing with water, the laminate was dipped inan electroless copper plating solution (CUST-2000 by Hitachi ChemicalCo., Ltd.) at 40° C. for 10 minutes. After washing with water, thelaminate was copper-plated in a copper sulfate plating solution (anadditive 0.2 ml/L-CC-1220 by Nikko Metal Plating Co., Ltd.) at 25° C.for 30 minutes at a current density of 2.5 A/dm². After washing withwater, the laminate was dried in a drying furnace at 100° C. for 30minutes, thereby forming a copper-plated layer 22 with a thickness ofabout 15 μm (FIG. 3( f)).

Next, an etching resist (H-9025K by Hitachi Chemical Co., Ltd.) waslaminated on each side of the laminate at 110° C. A film mask was placedon each etching resist in a closely contacted manner, and the mask wasirradiated with ultraviolet light from an ultra-high pressure mercurylamp at the rate of 120 mJ/cm². The laminate was then sprayed with adeveloping solution (10 g/L-sodium carbonate) at 30° C. for 20 secondsunder the pressure of 0.1 MPa. After washing with water, the laminatewas sprayed with an etching solution (250 g/L-copper (II) chloridedehydrate, 200 ml/L-hydrochloric acid) at 50° C. for 90 seconds underthe pressure of 0.2 MPa. After washing with water, the laminate wassprayed with a resist removal solution (30 g/L-sodium hydroxide) at 40°C. for 30 seconds under the pressure of 0.1 MPa in order to remove thedry film resist. The laminate was then washed with water and dried,thereby forming an outer-layer circuit 23 and manufacturing a four-layerbuild-up substrate 24 (FIG. 3 g).

Thus, in accordance with the present embodiment, a four-layer circuitboard comprising an inner-layer circuit formed by a composite member isprovided. The inner-layer circuit 19 comprising the composite member 16and the outer-layer circuit 23 comprising the copper-plated layer 22 areelectrically connected to one another by the close contact between thecopper 15 coating the composite member 16 and the copper-plated layer 22at the bottom of the via-hole. Thus, the iron-nickel alloy 14 and thecopper-plated layer 22 are not directly in close contact with oneanother. The same is true when the iron-nickel alloy is substituted withan iron-nickel-cobalt alloy.

In accordance with the present embodiment, the inner-layer circuitscomprise a power supply layer and a ground layer that are formed by thecomposite members, while the outer-layer circuits comprise a signallayer formed by the copper plating. One of the inner layers, that iseither the power supply layer or the ground layer, is connected to theouter layers on both sides.

In the four-layer circuit board manufactured in Embodiment 3, oneouter-layer circuit, one inner-layer circuit, and the other outer-layercircuit are electrically connected via 100 via-holes or through-holesthat are arranged in a daisy-chain pattern. In order to evaluate thereliability of the multilayer circuit board in terms of itslayer-to-layer electric interconnection, the circuit board was subjectedto a thermal shock cycle test consisting of 500 cycles of thermal cycletests from −55° C. for 30 minutes to 125° C. for 30 minutes, using athermal shock tester (NT1500 by Kusumoto Chemicals, Ltd.). Theinterconnection was judged as defective when the rate of change inresistance value has reached 10% or more from the initial resistancevalue, and the number of cycles at that time was recorded.

As a result, in the present embodiment, the rate of change of resistancevalue was not more than 10% even after 500 cycles, and thus no defectwas recognized. On the other hand, in a comparative example in which thelayer-to-layer interconnection was formed by plating the cross-sectionalsurface of the iron-nickel alloy exposed in the through hole, the rateof change exceeded 10% at 286 cycles.

Thus, by employing a structure where the iron-nickel alloy in thecomposite member is not directly plated for layer-to-layer electricinterconnection, a multilayer circuit board can be obtained that canmaintain an improved level of layer-to-layer electrical interconnectioneven when exposed to temperature changes caused by the activation of theelectric equipment.

Embodiment 4

FIG. 4 shows a cross-sectional view of the manufacturing process for amultilayer circuit board according to the invention. The steps describedin FIGS. 4( a) to 4(d) correspond to those of FIGS. 3( a) to (d).

A polyimide film with a thickness of about 50 μm having an electroplatedcopper foil 25 with a thickness of about 18 μm on one side thereof,similar to the one used in Embodiment 3, was set on either side of themember with the inner-layer circuit 19 formed thereon and laminatedusing a vacuum press, as shown in FIG. 4( e).

Then, the electroplated copper foil 25 was removed where a blindvia-hole was to be formed, using the above-mentioned etching solution(FIG. 4( f)).

A blind via-hole 21 of about φ100 μm was then formed using a carbondioxide gas laser drilling machine in a manner that the via-hole reachedthe surface of the copper 15 on each side but did not penetrate thecomposite member 16 (FIG. 4( g)).

The laminate was then treated with a desmearing solution at 70° C. forthree minutes, washed with water, treated with a neutralizer at 60° C.for five minutes, and then washed with water. The laminate was furthertreated with a plating catalyst solution at 25° C. for five minutes.After washing with water, the laminate was treated with an activator at25° C. for five minutes, washed with water, and then dried, whereby aplating catalyst was adhered. The laminate was then treated with anactivator at 25° C. for 30 seconds, washed with water, and then dippedin an electroless copper plating solution at 40° C. for 10 minutes.After washing with water, the laminate was copper-plated with a coppersulfate plating solution at 25° C. for 30 minutes at the current densityof 2.5 A/dm². After washing with water, the laminate was dried in adrying furnace at 100° C. for 30 minutes, thereby forming acopper-plated layer 22 with a thickness of about 15 μm, which isrelatively thin (FIG. 4( h)).

Thereafter, an etching resist was laminated on the laminate at 110° C.on either side. A film mask was then placed on the resist in a closelycontacted manner and irradiated with ultraviolet light from anultra-high pressure mercury lamp at 120 mJ/cm². After spraying thelaminate with a developing solution at 30° C. under the pressure of 0.1MPa for 20 seconds, the laminate was washed with water and sprayed withan etching solution at 50° C. under the pressure of 0.2 MPa for 90seconds. After washing with water, the laminate was then sprayed with aresist removal solution at 40° C. for 30 seconds under the pressure of0.1 MPa in order to remove the dry film resist. After washing withwater, the laminate was dried to form an outer-layer circuit 23, therebymanufacturing a four-layer build-up substrate 24 (FIG. 4( i)).

Thus, in accordance with the embodiment, the four-layer circuit boardcomprises inner-layer circuits formed by composite members. Theinner-layer circuit 19 formed by the composite member 16 is electricallyconnected with the outer-layer circuit 23 formed by the copper-platedlayer 22 by the close contact between the copper 15 coating thecomposite member 16 and the copper-plated layer 22 at the bottom of thevia-hole. Thus, the iron-nickel alloy 14 and the copper-plated layer 22are not directly in close contact with one another.

In accordance with the embodiment, the inner-layer circuits comprise apower supply layer and a ground layer that are formed by the compositemembers, while the outer-layer circuits comprise a signal layer formedby the copper plating. One of the inner layers, that is either the powersupply layer or the ground layer, is connected to the outer layer oneither side.

In the four-layer circuit board manufactured in Embodiment 4, oneouter-layer circuit is electrically connected to one inner-layercircuit, and then to the other outer-layer circuit via 100 via-holes orthrough-holes to form a daisy-chain pattern. In order to evaluate thereliability of layer-to-layer electrical interconnection, a 500-cyclethermal shock cycle test was conducted in the same manner as inEmbodiment 3, using the same evaluation standards. The results of thetest showed that the rate of change in resistance value after 500 cycleswas not more than 10%, thus indicating no abnormality.

Thus, by adopting the structure in which the iron-nickel alloy in thecomposite member is not directly in contact with the plating to providelayer-to-layer electrical interconnection, a multilayer circuit boardcan be obtained that can maintain a high level of reliability in termsof layer-to-layer electrical interconnection even when exposed totemperature changes caused by the activation of the electronicequipment.

COMPARATIVE EXAMPLE 1

The present comparative example concerns a four-layer circuit boardcomprising an inner-layer circuit made of a composite member and anouter-layer circuit made of copper plating. Hereafter, the process ofmanufacturing the circuit board will be described. The process includesthe step (FIG. 3( a)) of preparing an iron-nickel alloy through to thestep (FIG. 3( e)) of forming an insulating resin layer, as inEmbodiment 1. The subsequent steps are shown in FIG. 5 via schematiccross-sectional views. In the present comparative example, theinner-layer circuit was formed by a composite member and the outer-layercircuit was formed by plating. The same is true when the iron-nickelalloy is replaced with an iron-nickel-cobalt alloy.

Referring to FIG. 5( a), through holes 25 with about φ300 μm wereinitially drilled using an NC drilling machine. The laminate was thentreated with a desmearing solution (MLB-497 by Meltex) at 70° C. forfive minutes. After washing with water, the laminate was treated with aneutralizer (MLB-790 by Mltex) at 60° C. for five minutes, and thenwashed with water. The laminate was further treated with a platingcatalysis solution (HS-202B by Hitachi Chemical Co., Ltd.) at 25° C. forfive minutes. After washing with water, the laminate was then treatedwith an activator (ADP-601 by Hitachi Chemical Co., Ltd.) at 25° C. forfive minutes. The laminate was then washed with water and dried, wherebya plating catalyst was adhered thereto. Thereafter, the laminate wastreated with an activator (100 ml/L-sulfuric acid) at 25° C. for 30seconds. After washing with water, the laminate was subjected to adipping treatment in an electroless copper plating solution (CUST-2000by Hitachi Chemical Co., Ltd.) at 40° C. for 10 minutes. After washingwith water, the laminate was copper-plated with a copper sulfate platingsolution (an additive 0.2 ml/L-CC-1220, by Nikko Metal Plating Co.,Ltd.) at 25° C. for 30 minutes, with the current density of 2.5 A/dm².After washing with water, the laminate was dried in a drying furnace at100° C. for 30 minutes, thereby forming a copper-plated layer 26 with athickness of about 15 μm.

Then, an etching resist (H-9025K by Hitachi Chemical Co., Ltd.) waslaminated on each side as shown in FIG. 5( b) at 110° C., and then afilm mask was set on the resist in a closely contacted manner. Afterirradiating with ultraviolet light from an ultra-high pressure mercurylamp at 120 mJ/cm², the mask was sprayed with a developing solution (10g/L-sodium carbonate) at 30° C. for 20 seconds under the pressure of 0.1MPa. After washing with water, the laminate was sprayed with an etchingsolution (250 g/L-copper (II) chloride dehydrate, 200 ml/L-hydrochloricacid) at 50° C. for 90 seconds under the pressure of 0.2 MPa. Afterwashing with water, the laminate was sprayed with a resist removalsolution (30 g/L-sodium hydroxide) at 40° C. for 30 seconds under thepressure of 0.1 MPa in order to remove the dry film resist. The laminatewas then washed with water and dried, thereby forming an outer-layercircuit 27 and manufacturing a four-layer circuit board 28.

In the present comparative example, the four-layer circuit boardcomprises an inner circuit formed by a composite member. The inner-layercircuit 19 formed by the composite member 16 is electrically connectedto the outer-layer circuit 27 formed by the copper-plated layer 26 bythe close contact between the cross-section of the composite member 16and the copper-plated layer 26 of the through hole portion on the innerwall of the though hole. Thus, the iron-nickel alloy 14 and thecopper-plated layer 26 are in direct and close contact with one another.The same is true when the iron-nickel alloy 14 is substituted with aniron-nickel-cobalt alloy.

In the four-layer circuit board manufactured in the present comparativeexample, the same pattern as in Embodiment 3 is formed, and oneouter-layer circuit, one inner-layer circuit, and the other outer-layercircuit are electrically connected via 100 via-holes or through-holesthat are arranged in a daisy-chain pattern. In order to evaluate thereliability of layer-to-layer electrical interconnection, a thermalshock cycle test was conducted in the same manner as in Embodiment 3.

The results showed that in the comparative example, the rate of changereached 10% at 286 cycles. When the cross-section of the through holewhich has the highest resistance value of the through hole portion(layer-to-layer interconnection portion) was examined, a partial peelingof the copper plating from the iron-nickel alloy was observed. This wasdue to the cracking in the copper plating in the vicinity of theinterface between the iron-nickel alloy and the copper coating. Thecracking is the result of the severe nature of the thermal shock test,and the present characteristics can provide a sufficient level ofreliability.

In the present comparative example, the inner-layer circuits comprised apower supply layer and a ground layer that were formed by the compositemembers, while the outer-layer circuits comprised a signal layer formedby the copper plating. One of the inner layers, that is either the powersupply layer or the ground layer, was connected to the outer layers onboth sides.

COMPARATIVE EXAMPLE 2

FIG. 6 shows a cross-section of a multilayer circuit board employing acomposite member comprising an iron-nickel alloy having a copper platingon one side thereof, shown in FIG. 5. In the present comparativeexample, a four-layer circuit board was actually manufactured employinga composite member comprising an iron-nickel alloy with a coppercoating. The inner-layer circuits were formed by the composite memberscomprising a power supply layer and a ground layer, while theouter-layer circuits comprise a signal layer formed by copper plating.One of the inner layers, that is either the power supply layer or theground layer, was connected to the outer layer on either side. As shownin FIG. 6, when the through hole 33 was provided that has the copperplating 34, the connection portion 35 between the iron-nickel alloy 31and the copper plating 34 was subject to the stress caused by theirthermal expansion differences that manifest themselves as a result oftemperature changes that occur during actual operation. As a result, theconnection portion is slightly more likely to suffer the peeling of thecopper plating 34 from the iron-nickel alloy 31, an increase inconnection resistance, or defective electric connection, as comparedwith the above described Embodiments 1 to 4. The manufacturing processfor the present comparative example is the same as that for ComparativeExample 1. The same is true when the iron-nickel alloy is replaced withan iron-nickel-cobalt alloy.

Embodiment 5

FIG. 7 shows a plan view of the multilayer circuit board of theinvention near where a semiconductor device is to be mounted. FIG. 8shows a cross-sectional view of an electronic apparatus comprising thesubstrate of FIG. 7 on which a semiconductor device is mounted. Theelectronic apparatus according to this embodiment comprises themultilayer circuit board 40 obtained in any of Embodiments 1 to 6,wherein a semiconductor device 43 is directly bonded (bare chip mount)to connecting terminals 41 provided on the surface of the substrate 40via soldering balls 42. The two areas containing black dots areconnecting terminals 41 in a semiconductor device-mounted region 44where the semiconductor device 43 is to be mounted. Black squares andlines indicate wires 45. As shown in FIG. 8, the semiconductor device 43is directly bonded via the soldering balls 42. Numeral 46 designatescomponent terminals. In accordance with the present embodiment, byemploying a multilayer circuit board having a circuit layer comprising acomposite member that is formed by coating an iron-nickel alloy withcopper on one or both sides, an electronic apparatus can be obtainedthat can maintain a highly level of reliability in terms oflayer-to-layer electric interconnection in the multilayer circuit boardas well as electric connection between the semiconductor device and themultilayer circuit board even when exposed to temperature changes duringactual operation.

Thus, in accordance with the invention, a multilayer circuit board isemployed in which a circuit layer comprises a composite member formed bycoating an iron-nickel alloy with copper on at least one surfacethereof. Thus, the invention can provide a multilayer circuit board thatcan maintain a high level of reliability against temperature changesduring operation in terms of layer-to-layer electric interconnection, aprocess of manufacturing the same, a substrate for multilayer circuitry,and an electric apparatus.

1. An electronic apparatus comprising: a multilayer circuit board onwhich semiconductor devices are directly bonded, wherein said multilayercircuit board comprises: a laminate of at least one insulating layer anda plurality of wiring layers separated from one another by an insulatinglayer, wherein at least one of the wiring layers in the multilayercircuit board is formed by a composite material comprising a first metallayer and a second metal layer formed on one or both sides of the firstmetal layer, the first metal layer having a smaller coefficient ofthermal expansion than that of the second metal layer, the second metallayer having a higher electric conductivity than that of the first metallayer, wherein the insulating layer which is in contact with the secondmetal layer has a blind via-hole whose bottom portion is formed by asurface of the second metal layer, wherein the composite material andthe wiring layers are in layer-to-layer interconnection with one anotherthrough a layer-to-layer interconnection portion which is in contactwith the second metal layer formed in the blind via-hole.
 2. Theelectronic apparatus according to claim 1, wherein the first metal layeris iron-nickel alloy layer and the second metal layer is copper.
 3. Anelectronic apparatus comprising: a multilayer circuit board on whichsemiconductor devices are directly bonded, wherein said multilayercircuit board comprises: a laminate of at least one insulating layer anda plurality of wiring layers separated from one another by an insulatinglayer, wherein at least one of wiring layers in the multilayer circuitboard is formed by a process of manufacturing, wherein the process ofmanufacturing comprises the steps of: forming a wiring on the wiringlayer in a composite material comprising the wiring layer and theinsulating layer integrally formed on the wiring layer, the wiring layercomprising a second metal layer formed on one or both sides of a firstmetal layer, wherein the second metal layer has a larger coefficient ofthermal expansion than the first metal layer, forming a blind via-holein the insulating layer such that a bottom portion of the via-hole isformed by a surface of the second metal layer, and forming the compositematerial and the wiring layers in a layer-to-layer interconnection withone another through a layer-to-layer interconnection portion which is incontact with the second metal layer in the blind via-hole.
 4. Anelectronic apparatus comprising: a multilayer circuit board on whichsemiconductor devices are directly connected, wherein the multilayercircuit board comprises: a laminate of at least one insulating layer,and a plurality of wiring layers separated by an insulating layer,wherein at least one of wiring layers in the multilayer circuit board isformed by a composite material comprising a first metal layer and secondmetal layers formed on both sides of the first metal layer, the firstmetal layer having a smaller coefficient of thermal expansion than thatof the second metal layers, the second metal layers having a higherelectric conductivity than that of the first metal layer, wherein eachof the insulating layers facing one another via the composite materialhas a blind via-hole whose bottom portion is formed by a surface of thesecond metal layer, and a layer-to-layer interconnection portion on thesurface of the insulating layer and in each blind via-hole, wherein thelayer-to-layer interconnection portion in each blind via-hole is formedin such a manner as to be in contact with the second metal layersurface.
 5. The electronic apparatus according to claim 4, wherein thefirst metal layer is iron-nickel alloy layer and the second metal layeris copper.